IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2004 · 34 citations · 8 references
EngineeringComputer EngineeringElectrical EngineeringField-programmable Gate ArraysMicroelectronicsReconfigurable ComputingConfigurable Logic BlocksDigital Signal ProcessingField-programmable Gate Array ArchitectureFpga ArchitectureHardware AccelerationLookup TablesArea-efficient Fpga ArchitectureDigital Signal Processing BlocksField-programmable Gate Arrays (Fpgas)Lut RoutingLut-based Logic OptimizationMultiplier DesignMultipliers
A novel design technique for deriving highly efficient multipliers that operate on a limited range of multiplier values is presented. Using the technique, Xilinx Virtex field programmable gate array (FPGA) implementations for a discrete cosine transform and poly-phase filter were derived with area reductions of 31%-70% and speed increases of 5%-35% when compared to designs using general-purpose multipliers. The technique gives superior results over other fixed coefficient methods and is applicable to a range of FPGA technologies.
8