Lut Routing
LUT Routing is a configurable interconnection mechanism in field-programmable gate arrays that directs signals between lookup tables according to programmable routing constraints to enable logical function implementation.
44
Publications
1.4K
Citations
111
Authors
53
Institutions
Publications per year
2017–2026
6
Parents
44
The stratixπ routing and logic architecture
David Lewis, Vaughn Betz, David Jefferson et al. · 2003 · 157 citations
Engineering, Computer Engineering, Electrical Engineering +17
A test methodology for interconnect structures of LUT-based FPGAs
Hiroyuki Michinishi, Tokumi Yokohira, Tatsuki Okamoto et al. · 2002 · 85 citations · Full text
Using sparse crossbars within LUT
Guy Lemieux, David Lewis · 2001 · 72 citations
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University of California, Los Angeles
Los Angeles, United States
6 h-index
11 publications
194 citations
University of California, Berkeley
Berkeley, United States
3 h-index
3 publications
120 citations

University of Toronto
Toronto, Canada
3 h-index
7 publications
425 citations
University of Illinois Urbana-Champaign
Urbana, United States
2 h-index
2 publications
27 citations
Xilinx (United States)
San Jose, United States
2 h-index
4 publications
120 citations

Clarkson University
Potsdam, United States
2 h-index
2 publications
112 citations
UCLA Health
Los Angeles, United States
2 h-index
5 publications
136 citations

University of British Columbia
Vancouver, Canada
1 h-index
1 publications
10 citations
1–8 of 53
2 publications · 25 citations
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2 publications · 52 citations
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1 publications · 13 citations
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Conference · 1 publications · 18 citations
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ICCAD · 1 publications · 23 citations
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