A new retiming-based technology mapping algorithm for LUT-based FPGAs

Abstract

In this paper, w e presen t a new retiming-based technology mapping algorithm for look-up table-based field programmable gate arrays. The algorithm is based on a novel iterative procedure for computing all k-cuts of all nodes in a sequen tialcircuit, in the presence of retiming. The algorithm completely avoids flow computation whic his the bottleneck of previous algorithms. Due to the fact that k is very small in practice, the procedure for computing all k-cuts is v ery fast. Experimental results indicate the overall algorithm is very efficient in practice.