Monolithic 3D Integrated Circuits

TLDR

3D integrated circuits aim to overcome 2D communication limits and enable heterogeneous integration, with approaches ranging from chip stacking to full monolithic integration at varying maturity levels. The paper focuses on the monolithic 3D approach, highlighting its high‑density vertical interconnects for optimal transistor assembly while discussing the associated technology challenges. The study examines the monolithic 3D integration method, leveraging dense vertical interconnects to optimally assemble transistors and interconnects within a 3D volume. Performance benefits of monolithic 3D integration are shown using a 3D‑FPGA implementation.

Abstract

3D IC's promise to solve the 2D communication bottleneck, and enable the integration of heterogeneous materials, devices and systems. There are at least three approaches to realize 3D IC's : chip stacking, wafer stacking and full monolithic integration. Each approach is at a different level of maturity and offers various degree of improvement. This paper will focus on the monolithic 3D approach, which offers a high density of device-dimension vertical interconnects and thereby facilitates the optimal assembly of transistors and interconnects in a 3D volume. The performance advantages of such a technology are demonstrated with a 3D-FPGA. Technology challenges of monolithic approach are discussed.