Design and Fabrications of High Voltage IGBTs on 4H-SiC

Abstract

For the first time, SiC planar p-IGBTs with 5.8 kV of blocking voltage have been fabricated and characterized. The device exhibits a differential on-resistance of ~ 570 mOmegamiddotcm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at the gate bias of -30 V at 25degC, and decreases to ~ 118 mOmegamiddotcm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at 200degC, ~108 mOmega middot cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at 300degC, respectively. The median hole mobility in the inversion channel is 2.3 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vmiddots, and increases gradually with temperature. The effects of p-type field stopper layer and JFET region implantation to device current conduction capability were investigated. Numerical simulations have shown that to improve IGBT on-resistance, it is critical to achieve a high carrier lifetime in both drift region and JFET region, and a high value of inversion layer hole mobility