Advanced Surface Laminar Circuit Packaging with low Coefficient of Thermal Expansion and high wiring density

Abstract

Flip-chip bonding on organic sequential build-up substrate technology has been an essential part of semiconductor packaging. In the quest for an ever higher semiconductor performance there has been a rapid increasing need for a finer pitch area array flip-chip joints. However, the pitch has been limited by the packaging technology. Advanced Surface Laminar Circuit (Adv-SLC) packaging technology has been developed to satisfy the requirements for the most advanced semiconductor devices. Adv-SLC is a build-up substrate featuring a low Coefficient of Thermal Expansion (CTE) of 3 ppm/°C, a fine pattern of 8 µm in line width and spacing, plated through-holes of 100 µm in pitch and micro-vias of 25 °m in diameter. These features accommodate the density of a chip I/O of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−2</sup> , which is about ten times greater than that achieved in current organic packaging, and enables significant size reduction of semiconductor chips and the associated packages. The low CTE significantly reduces the strain in the solder joints during the reflow process and ensures the solder joint reliability. The CTE can be expanded to 5 ppm/°C by adjusting the volume ratio of the resin in the core. This paper describes recent progress in the development of Adv-SLC packaging technology.