1990 · 45 citations · 12 references
ComputingComputer EngineeringComputer ScienceCompilersComputer ArchitectureHardware-software Co-designCode GenerationCompiler ConstructionControl-flow AnalysisData-flow AnalysisInstruction Set ArchitectureRegister AllocationAllocation For Risc ArchitecturesGlobal Register AllocationModule ArchitectureRegister ArchitectureRegister AssignmentRegister File DesignRegister-level ProgrammingSpill Code Insertion
This paper describes a method for compiling programs using interprocedural register allocation. A strategy for handling programs built from multiple modules is presented, as well as algorithms for global variable promotion and register spill code motion. These algorithms attempt to address some of the shortcomings of previous interprocedural register allocation strategies. Results are given for an implementation on a single register file RISC-based architecture.
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Susan L. Graham, Peter B. Kessler, Marshall Kirk McKusick · 1982 · 978 citations
Register allocation & spilling via graph coloring
Gregory J. Chaitin · ACM SIGPLAN Notices · 1982 · 767 citations · Full text
Register allocation & spilling via graph coloring
Gregory J. Chaitin · 1982 · 668 citations
Register allocation by priority-based coloring
Frederick Chow, John L. Hennessy · 1984 · 219 citations
Global register allocation at link time
David W. Wall · ACM SIGPLAN Notices · 2004 · 207 citations