Head in pillow (HIP) and yield study on SIP and PoP assembly

Abstract

This paper uses a statistical approach to simulate the yield loss due to HIP (head-in-pillow) based on experimental work including production data. Detailed analyses on the HIP formation and mechanism were performed using Surface Evolver and optical measurement. Stackup analysis using statistical modeling and Monte Carlo simulation is performed to assess the magnitude of yield loss. From this study, it is learned that the warpage of package and PCB, solder paste printing, flux type and solder alloy, all play important roles in HIP formation. Both shadow moire measurement and finite element analysis (FEA) were conducted to characterize BGA and PCB warpage and offer guidance for effective control of the warpage. Finally, various effective options will be discussed to reduce the HIP defects. Interestingly enough, it is found that BGA warpage need to be controlled but the impact of PCB warpage is more complex.