IEICE Transactions on Electronics · 2005 · 19 citations · 5 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureLow-power DesignSystem-on-chip DesignField-programmable Gate Array ArchitectureLow-power Cache DesignLow-power Digital Circuit DesignMotion EstimationTiming AnalysisVideo AnalysisBlock EstimationDigital Signal Processing Block ArchitectureDigital Signal Processing BlocksPower ConsumptionPower Consumption OptimizationSystolic Array DesignSystolic ArraysVideo Compression
SUMMARY This paper proposes a low-power systolic array architecture for a block-matching motion estimation processor IP for portable and high-resolution video applications. The architecture features a ringconnected processing element (PE) array to reduce both computation cycles and memory access cycles at the same time, allowing lower power characteristics. The feature of low memory access cycles allows concurrent operation of a half-pel processing unit with no extra cache. Furthermore, the architecture allows various summation schemes for absolute difference values. For that reason, it is applicable to various video coding modes such as the adaptive field/frame mode in MPEG2 and multiple macroblock mode in H.264. When the architecture is introduced to a design of a MPEG2 MP@HL motion estimation processor VLSI, the power consumption of the VLSI is reduced by 45–73% in comparison to cases with conventional
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A half-pel precision motion estimation processor for NTSC-resolution video
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SuperENC: MPEG-2 video encoder chip
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