An 8.5 mW, 0.07 mm 2 ADPLL in 28 nm CMOS with sub-ps resolution TDC and < 230 fs RMS jitter

Abstract

An All-Digital PLL (ADPLL) in 28 nm CMOS is designed to generate low noise clocks for high-speed ADCs. A high-resolution (<; 1 ps), short-span (6 ps) Time-to-Digital Converter (TDC) is implemented to improve the phase noise with little cost of power and area. This ADPLL has <; 230 fs RMS jitter at 50 MHz reference frequency, with 8.5 mW power from 1.8V supply and an area of 0.07 mm2.