Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications

Abstract

This paper describes an integer-N BB-PFD DPLL architecture for wireline communication applications. The feasibility of the structure is demonstrated by implementations targeting applications in the 8-to-11 Gb/s and 17-to-20 Gb/s ranges. A key challenge associated with this approach is how to achieve the proportional-path latency and gain required for overall low-noise DPLL performance. In particular, it is well-known that the strong nonlinearity introduced by the BB-PFD manifests itself as a bounded limit cycle. This results in the DPLL output jitter to increase as the proportional path latency and gain increase. To minimize the negative effect of the limit cycle, the DPLL architecture features a separate low-latency proportional path, with the BB- PFD output directly controlling the DCO. Other features include controllability of the proportional-path gain and of the BBPFD gain.