Mark Chambers

A Low-Power Single-Weight-Combiner 802.11abg SoC in 0.13 µm CMOS for Embedded Applications Utilizing An Area and Power Efficient Cartesian Phase Shifter and Mixer Circuit

Ali Afsahi, J.J. Rael, Arya Behzad et al. · IEEE Journal of Solid-State Circuits · 2008 · 27 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 200 Mb/s PRML read/write channel IC

K. Parsi, N. Rao, R.L. Burns et al. · 2002 · 21 citations

Engineering, Computer Engineering, Electrical Engineering +13

An 8.5 mW, 0.07 mm 2 ADPLL in 28 nm CMOS with sub-ps resolution TDC and < 230 fs RMS jitter

Bo Shen, Greg Unruh, Marcel Lugthart et al. · 2013 · 20 citations

Engineering, Electrical Engineering, Analog Electronics +16

A 2.7 GHz to 7 GHz Fractional-N LC-PLL Utilizing Multi-Metal Layer SoC Technology in 28 nm CMOS

Changhyeon Lee, Lindel Kabalican, Yan Ge et al. · IEEE Journal of Solid-State Circuits · 2014 · 15 citations

Engineering, Electrical Engineering, Low-power Design +16

A 0.5–9.5-GHz, 1.2- $\mu \text{s}$ Lock-Time Fractional-N DPLL With ±1.25%UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling

Fazil Ahmad, Greg Unruh, Amrutha Iyer et al. · IEEE Journal of Solid-State Circuits · 2016 · 15 citations

Engineering, Computer Engineering, Electrical Engineering +17