An approach to high-level synthesis system validation using formally verified transformations

Abstract

Complexity of advanced high-level synthesis algorithms can be attributed to design quality concerns. However this complexity may lead to software errors in their implementations which may adversely impact design correctness. Transformational synthesis is a synthesis methodology where localized, behavior-preserving register transfer level (RTL) transformations are used to obtain a correct and constraint satisfying RTL design. This paper presents the novel use of a set of such transformations in validating an existing non-transformational synthesis system by discovering and to some extent isolating software errors.