Rtl Verification
RTL Verification is a formal process within digital system design that belongs to the class of hardware verification methodologies, specifically distinguished by its focus on validating the correctness of register-transfer level models with respect to functional specifications prior to logic synthesis.
239
Publications
6.1K
Citations
633
Authors
180
Institutions
Publications per year
2017–2026
32
Variants
Register-transfer Level Verification
239
Benchmarking Large Language Models for Automated Verilog RTL Code Generation
Shailja Thakur, Baleegh Ahmad, Zhenxing Fan et al. · 2023 · 142 citations
Kevin Laeufer, Jack Koenig, Donggyu Kim et al. · 2018 · 122 citations
1–5 of 239
633
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University of California, Santa Barbara, United States
6 publications · 223 citations
6
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6
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1–5 of 633
180
Intel (United States)
Santa Clara, United States
11 h-index
24 publications
496 citations
The University of Texas at Austin
Austin, United States
10 h-index
17 publications
381 citations
University of Verona
Verona, Italy
10 h-index
42 publications
870 citations
University of Illinois Urbana-Champaign
Urbana, United States
7 h-index
13 publications
261 citations
University of California, Santa Barbara
Santa Barbara, United States
6 h-index
18 publications
641 citations
Motorola (United States)
Schaumburg, United States
6 h-index
15 publications
279 citations
Stanford University
Stanford, United States
6 h-index
20 publications
526 citations
Synopsys (United States)
Mountain View, United States
6 h-index
17 publications
559 citations
1–8 of 180
9 publications · 194 citations
9
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7 publications · 231 citations
7
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7 publications · 138 citations
7
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5 publications · 161 citations
5
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3 publications · 35 citations
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1–5