Rtl Verification

RTL Verification is a formal process within digital system design that belongs to the class of hardware verification methodologies, specifically distinguished by its focus on validating the correctness of register-transfer level models with respect to functional specifications prior to logic synthesis.

239

Publications

6.1K

Citations

633

Authors

180

Institutions

Publications per year

2017–2026

32

Variants

Register-transfer Level Verification

Authors

633

  1. FF
    Franco Fummi

    University of Verona, Italy

    10 publications · 178 citations

    10

    h-index

  2. GP
    Graziano Pravadelli

    University of Verona, Italy

    11 publications · 260 citations

    10

    h-index

  3. NB
    Nicola Bombieri

    University of Verona, Italy

    12 publications · 270 citations

    10

    h-index

  4. KC
    Kwang‐Ting Cheng

    University of California, Santa Barbara, United States

    6 publications · 223 citations

    6

    h-index

  5. JA
    Jacob A. Abraham

    The University of Texas at Austin, United States

    6 publications · 110 citations

    6

    h-index

1–5 of 633

Venues

  1. 9

    h-index

  2. IEEE Transactions on Computers

    7 publications · 231 citations

    7

    h-index

  3. IEEE Design & Test of Computers

    7 publications · 138 citations

    7

    h-index

  4. 5

    h-index

  5. Design Automation for Embedded Systems

    3 publications · 35 citations

    3

    h-index

1–5