VLSI Implementations of Low-Power Leading-One Detector Circuits

Abstract

This paper presents two approaches to design leading-one detector (LOD) circuits, which locate the leading-one position in a binary word. The first approach provides fast leading-one detectors (LODs), and the second emphasizes the design of novel hardware-efficient and low-power LODs. Each approach is used to obtain 0.6 mum CMOS VLSI implementations of 16-, 32-, and 64-bit LOD circuits. Simulations of the 16-, 32-, and 64-bit fast LODs run at 310, 265, and 215 MHz, respectively. The 16-, 32-, and 64-bit low-power LODs consume 14.85, 44.70, and 61.67 milliwatts, respectively while operating at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD </sub> equal to 5 volts and their maximum speed