N<sup>3</sup>ASICs: Designing nanofabrics with fine-grained CMOS integration

Abstract

We propose a novel nanofabric approach that mixes unconventional nanomanufacturing with CMOS manufacturing flow and design rules in order to build a reliable nanowire-CMOS fabric called N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> ASIC with no new manufacturing constraints added. Active devices are formed on a dense uniform semiconductor nanowire array and standard area distributed pins/vias; metal interconnects route the signals in 3D. CMOS design rules are followed. Novel nanowire based devices are envisioned and characterized based on 3D physics modeling. Overall N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> ASIC fabric design, associated circuits, interconnection approach, and a layer-by-layer assembly sequence for the fabric are introduced. Key system level metrics such as power, performance, and density for a nanoprocessor design built using N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> ASICs were evaluated and compared against a functionally equivalent CMOS design synthesized with state-of-the-art CAD tools. We show that the N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> ASICs version of the processor is 3X denser and 5X more power efficient for a comparable performance than the 16-nm scaled CMOS version even without any new/unknown-manufacturing requirement added.