Error recovery technique for coarse-grained reconfigurable architectures

Abstract

This paper presents the implementation of the error recovery scheme from temporary faults, applicable for datapaths of coarse-grained reconfigurable architectures. We have chosen the DART architecture as a vehicle to study various aspects related to implementation of the instruction retry in a complex highly parallel reconfigurable system. Synthesis results have confirmed the time, hardware, and power consumption efficiency of the proposed approach, which can be applied independently on the concurrent error detection scheme actually used.