Stress migration reliability of wide CU interconnects with gouging vias

Abstract

Stress migration (SM) reliability of wide copper (Cu) interconnects with gouging vias was studied using a via chain structure stressed at temperatures ranging from 150/spl deg/C to 200/spl deg/C. After a 1000-hour SM test, via chain structures at the edge of the wafer were observed to have extremely high resistance due to the formation of stress-induced voids at the silicon nitride (Si/sub 3/N/sub 4/) cap/via interface around the perimeter of the gouging via and at the via bottom. One of the dominant causes for this phenomenon was attributed to the presence of process-induced weak points resulting from poor diffusion barrier layer coverage at the sidewall of the via bottom. In addition, a simulation model based on a three dimensional (3D) finite element analysis (FEA) was developed to study the stress distribution of a gouging via. The simulation results showed that high tensile stress was found at the Si/sub 3/N/sub 4/ cap/via interface around the perimeter of the gouging via. It is believed that at high temperature stressing, the presence of process-induced weak points, coupled with the high tensile stress, favor void nucleation. The steep stress gradient developed around the void vicinity after its nucleation was proposed to be the dominant driving force for subsequent vacancy accumulation and void growth extending beneath the gouging via, thus leading eventually to an open circuit. The effect of via gouging on the SM performance of Cu interconnects was also discussed.