Implementation of Cholesky LLT-Decomposition Algorithm in FPGA-Based Rational Fraction Parallel Processor

Abstract

In this paper, the fixed size processor array architecture, which is destined for realization of LL <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sup> -decomposition of symmetrical positively definite matrices based on Cholesky algorithm, is proposed. In order to implementation of this architecture in modern FPGA devices, the arithmetic unit (AU) operating in the rational fraction arithmetic is designed. This AU is adapted to realization in the Xilinx reconfigurable platforms Virtex II or Virtex 4 families and its hardware complexity is up to 4,5 times less in comparison with similar AUs operating with float-point numbers.