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VLSI array processors
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1988
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EngineeringComputer ArchitectureVlsi Array ProcessorsProcessor ArchitectureHardware SecurityArray ComputingSuch Array ProcessorsTomographic Signal ProcessingSystems EngineeringParallel Processor TechnologyParallel ComputingComputer EngineeringComputer ScienceMicroelectronicsSignal ProcessingArray ProcessingVlsi ArchitectureParallel ProgrammingVlsi
Real‑time digital signal processing requires high‑speed parallel processors, but general‑purpose systems suffer from overhead, making special‑purpose array processors the preferred solution. This article provides a general overview of VLSI array processors and a unified treatment from algorithm, architecture, and application perspectives. Array processors exploit the regularity, recursiveness, and local communication of signal‑processing algorithms, using innovative systolic and wavefront architectures that maximize VLSI’s computational density while mitigating communication bottlenecks.
High speed signal processing depends critically on parallel processor technology. In most applications, general-purpose parallel computers cannot offer satisfactory real-time processing speed due to severe system overhead. Therefore, for real-time digital signal processing (DSP) systems, special-purpose array processors have become the only appealing alternative. In designing or using such array Processors, most signal processing algorithms share the critical attributes of regularity, recursiveness, and local communication. These properties are effectively exploited in innovative systolic and wavefront array processors. These arrays maximize the strength of very large scale integration (VLSI) in terms of intensive and pipelined computing, and yet circumvent its main limitation on communication. The application domain of such array processors covers a very broad range, including digital filtering, spectrum estimation, adaptive array processing, image/vision processing, and seismic and tomographic signal processing, This article provides a general overview of VLSI array processors and a unified treatment from algorithm, architecture, and application perspectives.