Advanced Integration Process Technology for Highly Reliable Ferroelectric Devices

Abstract

The retention properties were improved by optimizing capacitor process and developing advanced integration process. The retention trends of ferroelectric capacitors before integration were systematically investigated as a function of critical process parameters such as baking temperature and annealing temperature and time. It was found that the ferroelectric capacitors show best retention properties by double annealing process with high baking temperature of 330°C. The optimized ferroelectric capacitors were integrated into 32 Mb FRAM with 0.44 μm2 cell size and 0.25 μm design rule, and evaluated for their retention behavior. Since the retention properties of real cell size capacitors were closely correlated with sensing window, it was focused on enhancing the sensing window by high etching slope and chemical mechanical planarization (CMP) process. It was demonstrated that the retention properties were greatly improved by using optimal capacitor process and advanced integration process.