Publication | Closed Access
Lateral and Vertical Scaling of <formula formulatype="inline"><tex Notation="TeX">$\hbox{In}_{0.7} \hbox{Ga}_{0.3}\hbox{As}$</tex></formula> HEMTs for Post-Si-CMOS Logic Applications
74
Citations
18
References
2008
Year
EngineeringIntegrated CircuitsSemiconductor DeviceSemiconductorsElectronic DevicesNanoelectronicsElectronic EngineeringLogic PerformanceDevice ModelingSemiconductor TechnologyElectrical EngineeringPhysicsVertical ScalingPost-si-cmos Logic ApplicationsMicroelectronicsElectronic MaterialsTechnology ScalingApplied PhysicsGate Delay
<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> In this paper, we have experimentally investigated the impact of lateral and vertical scaling of <formula formulatype="inline"><tex Notation="TeX">$\hbox{In}_{0.7}\hbox{Ga}_{0.3}\hbox{As}$</tex></formula> high-electron-mobility transistors (HEMTs) onto their logic performance. We have found that reducing the <formula formulatype="inline"><tex Notation="TeX"> $\hbox{In}_{0.52}\hbox{Al}_{0.48}\hbox{As}$</tex></formula> insulator thickness results in much better electrostatic integrity and improved short-channel behavior down to a gate length of around 60 nm. Our nearly enhancement-mode 60-nm HEMTs feature <formula formulatype="inline"><tex Notation="TeX">$V_{T} = -\hbox{0.02 V}$</tex></formula>, <formula formulatype="inline"><tex Notation="TeX">$\hbox{DIBL} = \hbox{93 mV/V}$</tex></formula>, <formula formulatype="inline"> <tex Notation="TeX">$S = \hbox{88 mV/V}$</tex></formula>, and <formula formulatype="inline"><tex Notation="TeX">$I_{\rm ON}/\break I_{\rm OFF} = \hbox{1.6} \times \hbox{10}^{4}$</tex></formula>, at <formula formulatype="inline"><tex Notation="TeX">$V_{\rm DD} = \hbox{0.5 V}$ </tex></formula>. We also estimate a gate delay of <formula formulatype="inline"><tex Notation="TeX">$CV/I = \hbox{1.6 ps}$</tex> </formula> at <formula formulatype="inline"><tex Notation="TeX">$V_{\rm DD} = \hbox{0.5 V}$</tex></formula>. We have benchmarked these devices against state-of-the-art Si CMOS. For the same leakage current, which includes the gate leakage current, the InGaAs HEMTs exhibit <formula formulatype="inline"><tex Notation="TeX">$\hbox{1.2}\times$</tex></formula> more current drive <formula formulatype="inline"><tex Notation="TeX">$(I_{\rm ON})$</tex></formula> than the state-of-the-art 65-nm low-power CMOS technology at <formula formulatype="inline"><tex Notation="TeX">$V_{\rm DD} = \hbox{0.5 V}$</tex></formula>. </para>
| Year | Citations | |
|---|---|---|
Page 1
Page 1