Patterning sub-30-nm MOSFET gate with i-line lithography

Abstract

We have investigated two process techniques: resist ashing and oxide hard mask trimming. A combination of ashing and trimming produces sub-30-nm MOSFET gates. These techniques require neither specific equipment nor materials. These can be used to fabricate experimental devices with line width beyond the limit of optical lithography or high-throughput e-beam lithography. They provide 25-nm gate patterns with i-line lithography and sub-30-nm pattern with e-beam lithography. A 40-nm gate channel length nMOSFET is demonstrated.