A simple punchthrough model for short-channel MOSFET's

Abstract

Punchthrough currents impose severe limitations on the minimum channel length and leakage currents of scaled MOS transistors. A simple model is proposed to calculate the low-level punchthrough characteristics. Taking into account the two-dimensional geometrical effects, this model calculates the drain-induced barrier-lowering (DIBL) and the punchthrough current as a function of the processing parameters, and the gate, drain, and substrate bias. Experiments on devices with substrate dopings 6 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">14</sup> and 6.6 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">15</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> and channel lengths from 1 to 2 µm show good agreement with the theory.