VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects

TLDR

Within‑die parameter variation limits microprocessor frequency and increases leakage power, posing a major design challenge. The paper proposes a microarchitecture‑aware process‑variation model and a timing‑error framework to support microarchitectural research. VARIUS combines a compact, intuitive variation model with an error model to produce detailed timing‑error statistics across process parameters and operating conditions. The model predicts microarchitectural block failure rates as a function of clock frequency and variation, enabling detailed timing‑error analysis.

Abstract

Within-die parameter variation poses a major challenge to high-performance microprocessor design, negatively impacting a processor's frequency and leakage power. Addressing this problem, this paper proposes a microarchitecture-aware model for process variation-including both random and systematic effects. The model is specified using a small number of highly intuitive parameters. Using the variation model, this paper also proposes a framework to model timing errors caused by parameter variation. The model yields the failure rate of microarchitectural blocks as a function of clock frequency and the amount of variation. With the combination of the variation model and the error model, we have VARIUS, a comprehensive model that is capable of producing detailed statistics of timing errors as a function of different process parameters and operating conditions. We propose possible applications of VARIUS to microarchitectural research.