Publication | Closed Access
Scalable selector architecture for x-tolerant deterministic BIST
38
Citations
16
References
2004
Year
Unknown Venue
EngineeringVlsi DesignComputer ArchitectureTest Data GenerationFormal VerificationHardware SecurityNovel Selector ArchitectureComputer EngineeringScalable Selector ArchitectureBuilt-in Self-testComputer ScienceDesign For TestingMutation-based TestingCircuit DesignX-tolerant Deterministic BistProgram AnalysisScan PatternsSoftware TestingFormal MethodsCombinatorial Testing Workflow
X-tolerant deterministic BIST (XDBIST) was recently presented as a method to efficiently compress and apply scan patterns generated by automatic test pattern generation (ATPG) in a logic built-in self-test architecture. In this paper we introduce a novel selector architecture that allows arbitrary compression ratios, scales to any number of scan chains and minimizes area overhead. XDBIST test-coverage, full X-tolerance and scan-based diagnosis ability are preserved and are the same as deterministic scan-ATPG.
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