2008 · 24 citations · 6 references
ComputingComputer EngineeringComputer ScienceComputer ArchitectureCryptographyReconfigurable ComputingCryptographic AlgorithmsCryptographic ArchitectureCryptographic HashingCryptographic ImplementationData EncryptionHardware AccelerationAdvanced Encryption StandardCryptographic Accelerator DesignData Encryption StandardsEncryptionEncryption AlgorithmsReconfigurable ArchitecturesReconfigurable CircuitsSecure Co-processor Design
Nowadays hi-tech secure products offer more services and more security. The corresponding market is now oriented towards more flexibility. As an answer we propose here a multi-algorithm cryptographic co-processor called Celator. A main processor entrusts to the Celator the cryptographic tasks like encrypting or decrypting data blocks using secret key encryption algorithms such as advanced encryption standard (AES) or data encryption standard (DES). Moreover Celator allows hashing data using the secure hash algorithms (SHA). These algorithms are frequently implemented in hi-tech secure products in software or in hardware mode. Celator corresponds to their flexible hardware implementation. Moreover an user can (under specific conditions) implement its own cryptographic algorithm in Celator. Celator can perform an AES encryption with a throughput of 47 Mbps, the DES encryption with a throughput of 26 Mbps, condense a 512 bit SHA message with a throughput of 36 Mbps. Finally we report performance comparisons among Celator, general purpose processors, and some dedicated and dynamically reconfigurable circuits.
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Side channel cryptanalysis of product ciphers
John Kelsey, Bruce Schneier, David Wagner et al. · Journal of Computer Security · 2000 · 260 citations
Celator: A Multi-algorithm Cryptographic Co-processor
Daniele Fronte, Annie Pérez, Eric Payrat · 2008 · 24 citations