Concepedia

Secure Co-processor Design

Secure Co-Processor Design is a hardware security paradigm that integrates an isolated, tamper-resistant processing unit within a microcontroller architecture to offload and securely execute sensitive operations, thereby ensuring confidentiality, integrity, and availability distinct from the primary processor’s execution environment.

27

Publications

1.9K

Citations

77

Authors

30

Institutions

Publications per year

2017–2026

5

Parents

Publications

27

Building a high-performance, programmable secure coprocessor

Sean W. Smith, Steve Weingart · Computer Networks · 1999 · 338 citations

, , +12

Pioneer

Arvind Seshadri, Mark Luk, Elaine Shi et al. · ACM SIGOPS Operating Systems Review · 2005 · 321 citations

, , +16

Pioneer

Arvind Seshadri, Mark Luk, Elaine Shi et al. · 2005 · 224 citations

, , +16

Security Issues for Cloud Computing

Kevin W. Hamlen, Murat Kantarcıoğlu, Latifur Khan et al. · International Journal of Information Security and Privacy · 2010 · 178 citations

, , +14

Secure coprocessors in electronic commerce applications

Bennet Yee, J. D. Tygar · 1995 · 138 citations

, , +17

1–5 of 27

Authors

77

  1. SW
    Sean W. Smith

    Dartmouth College, United States

    5 publications · 540 citations

    5

    h-index

  2. TP
    Thomas Pöppelmann

    Ruhr University Bochum, Germany

    2 publications · 50 citations

    2

    h-index

  3. CH
    Christian Hanser

    Infineon Technologies (Austria), Austria

    2 publications · 50 citations

    2

    h-index

  4. JD
    J. D. Tygar

    University of California, Berkeley, United States

    2 publications · 264 citations

    2

    h-index

  5. PK
    Pradeep K. Khosla

    Carnegie Mellon University, United States

    2 publications · 545 citations

    2

    h-index

1–5 of 77

Institutions

30

  1. Dartmouth College

    Hanover, United States

    3 h-index

    5 publications

    334 citations

  2. Royal Holloway University of London

    Egham, United Kingdom

    2 h-index

    4 publications

    100 citations

  3. Infineon Technologies (Austria)

    Villach, Austria

    2 h-index

    8 publications

    200 citations

  4. Carnegie Mellon University

    Pittsburgh, United States

    2 h-index

    2 publications

    264 citations

  5. Dartmouth Hospital

    Dartmouth, United Kingdom

    2 h-index

    4 publications

    280 citations

  6. KU Leuven

    Leuven, Belgium

    2 h-index

    5 publications

    125 citations

  7. IBM (United States)

    Armonk, United States

    2 h-index

    3 publications

    997 citations

  8. Cisco Systems (China)

    Hong Kong, China

    1 h-index

    1 publications

    27 citations

1–8 of 30

Venues

  1. Computer Networks

    2 publications · 348 citations

    2

    h-index

  2. 1

    h-index

  3. IEEE Design and Test

    1 publications · 27 citations

    1

    h-index

  4. ACM Transactions on Embedded Computing Systems

    TECS · 1 publications · 19 citations

    1

    h-index

  5. Smart Card Research and Advanced Application Conference

    Conference · 1 publications · 18 citations

    1

    h-index

1–5