Integration Technology of 30nm Generation Multi-Level NAND Flash for 64Gb NAND Flash Memory

Abstract

Multi-level NAND flash memories with a 38nm design rule have been successfully developed for the first time. A break-through patterning technology of Self Aligned Double Patterning (SADP) together with ArF lithography is applied to three critical lithographic steps. Other key integration technologies include low thermal budget ILD process and twisted bit-line contact for excellent isolation between adjacent bit lines. Hemi-Cylindrical FET (HCFET) together with charge trapping memory cell of Si/SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> /SiN/Al <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> O <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> /TaN (TANOS) was found to be effective in sufficing various electrical requirements of 30nm generation flash cells. Finally, MLC operation is successfully demonstrated with flash cells of 8Gb density in which all the technologies aforementioned are combined.