A Timing Verification System Based on Extracted MOS/VLSI Circuit Parameters

Abstract

The Path Analysis program provides logic and circuit design checking for signal propagation delay constraints. The program is useful for optimizing network performance. Checking and optimization are traditionally performed by manual inspection and incompletely verified by logic and circuit simulation. The Path Analysis program completely verifies signal propagation delays against design constraints. Checks are performed either with user supplied logic simulation data or parameters extracted from the physical IC layout information.