Differential ring oscillators with multipath delay stages

Abstract

This work presents a differential ring oscillator architecture along with a design methodology that yields a compact, well-matched layout. A process independent attribute called the effective number of stages quantifies performance trade-offs in speed, jitter and power consumption. Design guidelines eliminate undesired modes of operation and guarantee robust differential oscillation. Theoretical predictions for four, five and six stage oscillators agree with measurements of CMOS 90nm and 0.13/spl mu/m implementations operating from 25 MHz to 6 GHz.