Optimization of phase-locked loop circuits via geometric programming

Abstract

We describe the global optimization of phase-locked loop (PLL) circuits using geometric programming (GP). Equations for the jitter, frequency range, and power of the PLL are presented in GP form. An array of PLL circuits was automatically generated using this technique in a 0.18 /spl mu/m, 1.8 V CMOS process. Silicon measurements show good agreement with the model. The results include a 1.9 GHz PLL with a period jitter of 2.2 ps RMS and an accumulated jitter of 6.2 ps RMS, consuming 10.8 mW.