Concepedia

Two step Deposited Rugged Surface (TDRS) Storagenode and Self Aligned Bitline-Contact-Penetrating Cellplate (SABPEC) for 64MbDRAM STC Cell

Hidenori Itob, Y. Miyagawa, Masaru Takahashi, T. Mitsuhashi, Yukifumi Kimura, Akira Endoh, Y. Nagatomo, Masaki Yoshimaru, F. Ichikawa, M. Ino

1991 · 11 citations · 2 references

DOI

Concepts

EngineeringComputer EngineeringMaterials ScienceSemiconductor DevicesSemiconductor MaterialsSurface EngineeringSemiconductor Device MaterialsSurface ModificationHigh-density Memory IntegrationMemory Cell DesignSelf-aligned Structures

Abstract

In this paper, the 1.5mum2 STC is reported with Two step Deposited Rugged Surface Poly-Si (TDRS) enabling fin shape storagenode and also with a Self-Aligned Bitline-contact by PEnetrating Cellplate (SABPEC) to increase projective storagenode area, reducing pattern tolerance.

References

2

Rugged surface poly-Si electrode and low temperature deposited Si/sub 3/N/sub 4/ for 64 Mbit and beyond STC DRAM cell

Masaki Yoshimaru, J. Miyano, Noriyuki Inoue et al. · 2002 · 19 citations

Engineering, Materials Engineering, Materials Science +17

A 1.28 &amp;mu;m<sup>2</sup> bit-line shielded memory cell technology for 64 Mb DRAMs

Y. Kawamoto, T. Kaga, Takashi Nishida et al. · 1990 · 11 citations

Engineering, Computer Engineering, Electrical Engineering +12