An EPR4 read/write channel with digital timing recovery

Abstract

This paper presents a device that uses digital interpolation of asynchronously sampled data to perform timing recovery. Analog-to-digital conversion (ADC) and finite impulse response filter (FIR) latency do not contribute to loop delay, moving most of the pulse equalization to the digital FIR. By eliminating the variable frequency oscillator, crosstalk is eliminated. Very low oversampling rates are shown to be sufficient, enabling data recovery at a low rate loss. Calibration modes for low-pass filter tuning and the flash ADC are used to improve performance of the analog channel. The 0.35-/spl mu/m CMOS device is specified for data rates up to 245 Mbps.