James Bailey

A 112-Gb/s PAM-4 Low-Power Nine-Tap Sliding-Block DFE in a 7-nm FinFET Wireline Receiver

James Bailey, Hossein Shakiba, Ehud Nir et al. · IEEE Journal of Solid-State Circuits · 2021 · 42 citations

Low-power Electronics, Electrical Engineering, Engineering +11

A 200 Mb/s CMOS EPRML channel with integrated servo demodulator for magnetic hard disks

Jonathan Fields, P.M. Aziz, James Bailey et al. · 2002 · 32 citations

Magnetic Hard Disks, Electrical Engineering, Pr4 Architecture +13

30.5 A 1.41pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS

Shayan Shahramian, Behzad Dehlaghi, Joshua Liang et al. · 2019 · 31 citations

Low-power Electronics, Hardware Security, Electrical Engineering +11

A Study of Discrete Multitone Modulation for Wireline Links Beyond 100 Gb/s

Behraz Vatankhahghadim, Nijwm Wary, James Bailey et al. · IEEE Open Journal of Circuits and Systems · 2021 · 28 citations · Full text

Wireless Communications, Engineering, Transmission System +20

A 1.41-pJ/b 56-Gb/s PAM-4 Receiver Using Enhanced Transition Utilization CDR and Genetic Adaptation Algorithms in 7-nm CMOS

Behzad Dehlaghi, Kerry Tang, Anthony Chan Carusone et al. · IEEE Solid-State Circuits Letters · 2019 · 21 citations

Engineering, Decision-feedback Equalizer, Jitter Tolerance +11