Joshua Liang

A 22.5-to-32-Gb/s 3.2-pJ/b Referenceless Baud-Rate Digital CDR With DFE and CTLE in 28-nm CMOS

Wahid Rahman, Danny Yoo, Joshua Liang et al. · IEEE Journal of Solid-State Circuits · 2017 · 66 citations

Engineering, Computer Engineering, Electrical Engineering +15

30.5 A 1.41pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS

Shayan Shahramian, Behzad Dehlaghi, Joshua Liang et al. · 2019 · 31 citations

Engineering, Computer Engineering, Electrical Engineering +17

A frequency-scalable 15-bit incremental ADC for low power sensor applications

Joshua Liang, D.A. Johns · 2010 · 26 citations

Engineering, Electrical Engineering, Analog Electronics +16

Loop Gain Adaptation for Optimum Jitter Tolerance in Digital CDRs

Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura et al. · IEEE Journal of Solid-State Circuits · 2018 · 23 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 1.41-pJ/b 56-Gb/s PAM-4 Receiver Using Enhanced Transition Utilization CDR and Genetic Adaptation Algorithms in 7-nm CMOS

Behzad Dehlaghi, Kerry Tang, Anthony Chan Carusone et al. · IEEE Solid-State Circuits Letters · 2019 · 22 citations

Engineering, Computer Engineering, Electrical Engineering +17