A digital read/write channel with EEPR4 detection

Abstract

This device increases the inter-symbol interference (ISI) manageable in a magnetic-media read channel. It re-configures analog and digital circuits by registers to optimize read and write channels. The 51 mm/sup 2/ device is fabricated in a standard 0.8 /spl mu/m single-poly double-metal CMOS process, and contains 128 k transistors. No external components are required for operation other than standard decoupling capacitors. Most of the circuits are active while reading data from the media (data mode), and techniques such as the use of differential analog structures, dedicated supply routes and substrate connections, and shields are employed to control digital interference.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>