Combining technology mapping with post-placement resynthesis for performance optimization

Abstract

This paper presents an innovative two-phase approach which combines technology mapping with logic resynthesis for minimizing the post-placement delays. The main idea is to alleviate the effect of inaccurate delay models in the mapping phase and to use a more accurate post-placement delay model in the logic resynthesis phase. To achieve this, our mapping phase disables the operations which may provide unpredictable effects on the circuit performance and leave them to be solved in the resynthesis phase. In the resynthesis phase, a post-placement delay model is extracted from the placement of the circuits. The techniques developed in our resynthesis algorithm are remapping, signal substitution, and gate duplication. Based on a wide range of benchmark examples, experimental results show that our approach provides 17% reduction in terms of post-placement delays when compared with SIS-1.2.