2006 · 68 citations · 35 references
ComputingComputer EngineeringComputer ScienceParallel ComputingReconfigurable ComputingStorage SystemsCache Behavior AnalysisCachingChainsDatapath DesignDatapath ModelingDynamic Load EffectsRegister File DesignShort-circuitingStore-to-load ForwardingUse-definition Chains
This paper presents NoSQ (short for no store queue), a microarchitecture that performs store-load communication without a store queue and without executing stores in the out-of-order engine. NoSQ implements store-load communication using speculative memory bypassing (SMB), the dynamic short-circuiting of DEF-store-load-USE chains to DEF-USE chains. Whereas previous proposals used SMB as an opportunistic complement to conventional store queue-based forwarding, NoSQ uses SMB as a store queue replacement. NoSQ relies on two supporting mechanisms. The first is an advanced store-load bypassing predictor that for a given dynamic load can predict whether that load will bypass and the identity of the communicating store. The second is an efficient verification mechanism for both bypassed and non-bpyassed loads using in-order load re-execution with an SMB-aware store vulnerability window (SVW) filter. The primary benefit of NoSQ is a simple, fast datapath that does not contain store-load forwarding hardware; all loads get their values either from the data cache or from the register file. Experiments show that this simpler design - despite being more speculative - slightly outperforms a conventional store-queue based design on most benchmarks (by 2% on average)
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The Alpha 21264 microprocessor
R. E. Kessler · IEEE Micro · 1999 · 863 citations
Memory dependence prediction using store sets
George Chrysos, Joel Emer · 1998 · 291 citations
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Memory dependence prediction using store sets
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