Store-to-load Forwarding

Store-to-Load Forwarding is a microarchitectural optimization technique in out-of-order execution processors that enables a load instruction to directly obtain data from a preceding store instruction in the memory dependence prediction structure before it commits, thereby reducing memory access latency by bypassing the cache hierarchy when the store and load addresses match.

Publications

1.2K

Citations

Authors

Institutions

Publications per year

2017–2026

Variants

Store-to-load Bypassing

Parents

Out-of-order Execution

Publications

Checkpoint processing and recovery: towards scalable large instruction window processors

Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan · 2003 · 271 citations

Engineering, Computer Engineering, Computer Science +17

Checkpoint processing and recovery: towards scalable large instruction window processors

Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan · 2004 · 149 citations

Engineering, Computer Engineering, Computer Science +17

Predictive techniques for aggressive load speculation

Glenn Reinman, Brad Calder · 1998 · 77 citations

Engineering, Computer Engineering, Computer Science +12

Scalable Store-Load Forwarding via Store Queue Index Prediction

Tingting Sha, Milo M. K. Martin, Aaron Roth · 2006 · 69 citations · Full text

Computing, Computer Engineering, Computer Systems +13

NoSQ: Store-Load Communication without a Store Queue

Tingting Sha, Milo M. K. Martin, Amir Roth · 2006 · 68 citations · Full text

Computing, Computer Engineering, Computer Science +13

1–5 of 22

Authors

MM
Milo M. K. Martin
University of Pennsylvania, United States
3 publications · 149 citations
3
h-index
ST
Srikanth T. Srinivasan
Intel (United States), United States
3 publications · 444 citations
3
h-index
BC
Brad Calder
University of California San Diego, United States
3 publications · 160 citations
3
h-index
GR
Glenn Reinman
University of California, Los Angeles, United States
3 publications · 160 citations
3
h-index
RR
Ravi Rajwar
Intel (United States), United States
3 publications · 444 citations
3
h-index

1–5 of 44

Institutions

1–8 of 17

Venues

ACM SIGARCH Computer Architecture News
2 publications · 53 citations
2
h-index
ACM Transactions on Architecture and Code Optimization
TACO · 1 publications · 24 citations
1
h-index
IBM Journal of Research and Development
1 publications · 40 citations
1
h-index
International Journal of Parallel Programming
1 publications · 10 citations
1
h-index
Proceedings of the ... annual International Symposium on Microarchitecture/Proceedings of the annual International Symposium on Microarchitecture
MICRO · 1 publications · 57 citations
1
h-index

1–5