Self-Aligned Fin-On-Oxide (FOO) FinFETs for Improved SCE Immunity and Multi-VTH Operation on Si Substrate

Abstract

The paper proposed a simple and novel approach to fabricate Fin-On-Oxide (FOO) FinFETs on silicon (Si) substrates for improved electrical characteristics in scaled devices. Based on conventional bulk-Si FinFET integration flow, a special step of a fin notch etching is performed, followed by a process of liner oxidation and isolation-oxide filling and recess. The fin above the notch is physically isolated from the substrate and turns into a self-aligned FOO structure. The fabricated p-type FOO FinFETs have demonstrated excellent short-channel effect (SCE) characteristics with subthreshold slope (SS) of 69 mV/dec and drain-induced barrier lowering (DIBL) of 22 mV/V for a physical gate length (LG) of 27 nm. For 14 nm devices, SS of 86 mV/dec and DIBL of 106 mV/V have been achieved, which are much better than those of the bulk-silicon FinFET counterpart with similar process. Meanwhile, the steady threshold voltage (VTH) shifting by the substrate biasing is realized in the FOO FinFET without performance degradations. The linearity of the VTH on the bias voltage is −6 mV/V. The self-aligned FOO-FinFET with a simple process provides a promising method to improve the SCE immunity as well as provides the multi-VTH operation for the scaled FinFET on Si substrates for future ultra-low power circuit applications.