IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2003 · 27 citations · 14 references
EngineeringComputer ScienceDigital DesignComputer ArchitectureField-programmable Gate ArraysReconfigurable ComputingDigital Logic DesignField-programmable Gate Array ArchitectureFpga ArchitectureLogic SynthesisRoutingRouting AlgorithmsBoolean SatisfiabilityBoolean Satisfiability ProblemEmulationFpga Routing AlgorithmsInput VariablesLogic Gate NetworksRouting In Field-programmable Gate ArraysSatisfiability
This paper presents a satisfiability-based method for solving the board-level multiterminal net routing problem in the digital design of clos-folded field-programmable gate array (FPGA) based logic emulation systems. The approach transforms the FPGA board-level routing task into a Boolean equation. Any assignment of input variables that satisfies the equation specifies a valid routing. We use two of the fastest Boolean satisfiability (SAT) solvers: Chaff and DLMSAT to perform our experiments. Empirical results show that the method is time-efficient and applicable to large layout problem instances.
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Matthew W. Moskewicz, Conor Madigan, Ying Zhao et al. · 2001 · 2.9K citations
Building and using a highly parallel programmable logic array
Maya Gokhale, William T. Holmes, A. Kopser et al. · Computer · 1991 · 202 citations