On Performance Testing with Path Delay Patterns

Abstract

Application specific ICs are typically designed to meet a given performance specification. For these ICs a higher performance does not add value and less performance makes the IC useless. This class of ICs is designed based on worst-case corner analysis. It is expected that this will become area costly in more advanced technologies. An alternative is to use statistical design techniques but this implies that the performance needs to be tested with, for example, path delay testing. Our experiments in 65 nm show that the actual delay depends on the global activity within an IC as well as effects in the local neighbourhood of the path. These global and local effects can independently cause about 15% of additional delay. Hence, their impact needs to be included during test and thr authors propose to create (close to) worst-case delay patterns. Individually, the patterns have an enhanced sensitivity for the most important local effects and combined they provide coverage for global effects. This makes them better suited as speed indicators than conventional path delay patterns.