Vertical Enhancement-Mode InAs Nanowire Field-Effect Transistor With 50-nm Wrap Gate

Abstract

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> We present results on fabrication and dc characterization of vertical InAs nanowire wrap-gate field-effect transistor arrays with a gate length of 50 nm. The wrap gate is defined by evaporation of 50-nm Cr onto a 10-nm-thick <formula formulatype="inline"><tex>$\hbox{HfO}_{2}$</tex></formula> gate dielectric, where the gate is also separated from the source contact with a 100-nm <formula formulatype="inline"><tex>$\hbox{SiO}_{x}$</tex> </formula> spacer layer. For a drain voltage of 0.5 V, we observe a normalized transconductance of 0.5 S/mm, a subthreshold slope around 90 mV/dec, and a threshold voltage just above 0 V. The highest observed normalized on current is 0.2 A/mm, with an off current of 0.2 mA/mm. These devices show a considerable improvement compared to previously reported vertical InAs devices with <formula formulatype="inline"><tex>$\hbox{SiN}_{x}$</tex></formula> gate dielectrics. </para>