IEEE Transactions on Circuits & Systems II Express Briefs · 2008 · 36 citations · 10 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureMicroelectronicsSystem-on-chip DesignCmos Circuit DesignDigital Logic DesignDigital Signal ProcessingLogic SynthesisCmos ScalingDigital Signal Processing BlocksFast Fourier TransformFast Fourier Transform Circuit DesignFourier TransformGate Logic AnalysisLogic OptimizationThroughput
In this study, an improved butterfly structure and an address generation method for fast Fourier transform (FFT) are presented. The proposed method uses reduced logic to generate the addresses, avoiding the parity check and barrel shifters commonly used in FFT implementations. A general methodology for radix-2 N-point transforms is derived and the signal flow graph for a 16-point FFT is presented. Furthermore, as a case study, a 16-point FFT with 32-bit complex numbers is synthesized using a CMOS 0.18 mum technology. The circuit gate count analysis indicates that significant logic reduction can be achieved with improved throughput compared to the conventional implementations.
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