Gate Logic Analysis
Gate Logic Analysis is a formal analytical method within fault tree analysis that specifies the logical relationships between system events through standardized logic gates, distinguishing it from other fault tree components by its focus on the structural and Boolean modeling of fault propagation pathways.
21
Publications
831
Citations
53
Authors
26
Institutions
Publications per year
2017–2026
2
Parents
21
A new approach to solve dynamic fault trees
Suprasad V. Amari, Glenn Dill, E. Howald · 2003 · 115 citations
1–5 of 21
53
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1–5 of 53
26
Wuhan University of Technology
Wuhan, China
2 h-index
6 publications
146 citations
University of California, Santa Barbara
Santa Barbara, United States
1 h-index
2 publications
76 citations
Université de Lille
Lille, France
1 h-index
3 publications
30 citations
Amirkabir University of Technology
Tehran, Iran
1 h-index
2 publications
28 citations
University of Houston
Houston, United States
1 h-index
1 publications
31 citations

University of Waterloo
Waterloo, Canada
1 h-index
2 publications
36 citations
National Fisheries University
Shimonoseki, Japan
1 h-index
2 publications
104 citations
Voies navigables de France
Béthune, France
1 h-index
1 publications
10 citations
1–8 of 26
3 publications · 76 citations
3
h-index
3 publications · 189 citations
3
h-index
2 publications · 66 citations
2
h-index
1 publications · 20 citations
1
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1 publications · 14 citations
1
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1–5