Gate Logic Analysis

Gate Logic Analysis is a formal analytical method within fault tree analysis that specifies the logical relationships between system events through standardized logic gates, distinguishing it from other fault tree components by its focus on the structural and Boolean modeling of fault propagation pathways.

21

Publications

831

Citations

53

Authors

26

Institutions

Publications per year

2017–2026

2

Authors

53

  1. SZ
    Siwei Zhou

    Wuhan University of Technology, China

    2 publications · 48 citations

    2

    h-index

  2. JX
    Jianwen Xiang

    Wuhan University of Technology, China

    2 publications · 48 citations

    2

    h-index

  3. MM
    M.R. Movahedin

    University of Tehran, Iran

    1 publications · 16 citations

    1

    h-index

  4. EJ
    Ernest J. Henley

    University of Houston, United States

    1 publications · 31 citations

    1

    h-index

  5. SX
    Shengwu Xiong

    Wuhan University of Technology, China

    1 publications · 25 citations

    1

    h-index

1–5 of 53

Venues

  1. IEEE Transactions on Reliability

    3 publications · 76 citations

    3

    h-index

  2. Reliability Engineering & System Safety

    3 publications · 189 citations

    3

    h-index

  3. 2

    h-index

  4. Nonlinear Analysis Hybrid Systems

    1 publications · 20 citations

    1

    h-index

  5. Microelectronics Reliability

    1 publications · 14 citations

    1

    h-index

1–5