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Chip-to-package interaction for a 90 nm Cu / PECVD low-k technology
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2004
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Chip-to-package InteractionNm TechnologyElectrical EngineeringOrganic PackagesEngineeringChip-scale PackageAdvanced Packaging (Semiconductors)Wafer Scale ProcessingNanoelectronicsChip On Board3D Ic ArchitectureApplied PhysicsSicoh Beol InsulatorComputer EngineeringElectronic PackagingMicroelectronicsOptoelectronicsInterconnect (Integrated Circuits)
A summary of chip-to-package interaction (CPI) evaluations for a 90 nm PECVD low k technology will be discussed. This review will cover a 90 nm technology that uses Cu dual damascene interconnections with a SiCOH (K /spl sim/ 3.0) CVD BEOL insulator stack across multiple wirebond package types and flipchip C4 ceramic and organic packages. It will be shown that with the use of IBM's internally engineered SiCOH BEOL insulator, CPI is not an issue with this technology node.