A deep sub-micron timing measurement circuit using a single-stage Vernier delay line

Abstract

On-chip timing and jitter measurement is one of the major challenges in recent years for characterizing high-speed analog and mixed-signal circuits. Although the Vernier delay line (VDL) method is a common approach to provide high timing resolution, its performance is limited by differential nonlinearity timing errors created by component mismatches. In this paper, a single-stage VDL approach is proposed in an attempt to reduce element-matching requirements. A custom IC was designed and fabricated in a 0.18 /spl mu/m CMOS process. The design requires a silicon area of 0.12 mm/sup 2/ and measured results indicate a timing resolution of 67 ps.