Bias-Stress-Induced Instability of Polymer Thin-Film Transistor Based on Poly(3-Hexylthiophene)

Abstract

A polymer thin-film transistor (PTFT) based on poly(3-hexylthiophene) (P3HT) is fabricated by a spin-coating process and characterized. Its bias-stress-induced instability during operation is investigated as a function of time and temperature. For negative gate-bias stress, the carrier mobility remains unchanged, the off-state current decreases, and the threshold voltage shifts toward the negative direction. On the other hand, for negative drain-bias stress, the carrier mobility decreases slightly, the off-state current increases, and the threshold voltage shifts toward the positive direction. The threshold shifts under gate- and drain-bias stresses are observed to be logarithmically dependent on time, and the decay rate of the threshold-voltage shift is independent of temperature. The results suggest that the origin of the threshold-voltage shift upon negative gate-bias stress is predominantly associated with holes trapped within the gate dielectric or at the interface, while time-dependent charge trapping in the deep trap states and creation of defect states in the channel region are responsible for the drain-bias stress effect on the PTFT.