IEEE Transactions on Nuclear Science · 1996 · 10 citations · 5 references
EngineeringComputer EngineeringComputer ScienceAnalog ElectronicsComputer ArchitectureField-programmable Gate ArraysConfigurable Logic BlocksEmbedded Memory BlocksField-programmable Gate Array ArchitectureMemory DevicesMemory Protection HardwareMemory Subsystem DesignData TaggingDigitizationField-programmable Gate Arrays (Fpgas)Memory Circuit DesignMemory Interface ArchitectureMemory Interface DesignRead-write CoordinationWrite Protection
A programmable analog memory address list manager has been developed for use with all analog memory-based detector subsystems of PHENIX. The unit provides simultaneous read/write control, cell write-over protection for both a Level-1 trigger decision delay and digitization latency, and re-ordering of AMU addresses following conversion, at a beam crossing rate of 105 ns. Addresses are handled such that up to 5 Level-1 (LVL-1) events can be maintained in the AMU without write-over. Data tagging is implemented for handling overlapping and shared beam-event data packets. Full usage in all PHENIX analog memory-based detector subsystems is accomplished by the use of detector-specific programmable parameters-the number of data samples per valid LVL-1 trigger and the sample spacing. Architectural candidates for the system are discussed with emphasis on implementation implications. Details of the design are presented including application specifics, timing information, and test results from a full implementation using field programmable gate arrays (FPGAs).
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Monolithic circuits for the WA98 lead class calorimeter
A.L. Wintenberg, T. C. Awes, C.L. Britton et al. · 2002 · 21 citations